What It Is
RISC-V (pronounced “risk-five”) is an instruction set architecture (ISA) — the fundamental specification that defines what commands a processor understands and how software instructs hardware to do work. Every general-purpose computer contains a processor built around one of a handful of dominant ISAs: Intel and AMD processors use the x86 architecture; smartphones and most modern non-Intel laptops use Arm. To build a chip using either, a manufacturer must license the architecture from its owner and pay royalties. RISC-V breaks that model entirely.
Created at the University of California, Berkeley in 2010 by a team led by Professor Krste Asanović and graduate students Andrew Waterman and Yunsup Lee, RISC-V was the fifth RISC architecture developed at Berkeley — hence the Roman numeral. The specification was published as open source in 2011. Any organisation, government, or individual can design a processor that implements RISC-V with no royalties, no licence fees, and no ongoing relationship with any controlling party. The architecture is also modular: a mandatory base instruction set can be supplemented with optional extensions for floating-point arithmetic, cryptography, vector processing, and AI acceleration, allowing RISC-V to scale from a microcontroller in an IoT sensor to a datacenter server chip.
The standard is maintained by RISC-V International, a Swiss nonprofit association that manages the specification, certifies compatibility, and governs the standards process. Its Swiss incorporation was deliberate: in November 2019, the organisation relocated from the United States specifically to remove itself from US export control jurisdiction, citing concerns about geopolitical disruption to open collaboration. As of 2025, it counts approximately 4,600 members across 70 countries.
Why It Matters for AI Governance and Narratives
RISC-V sits at the intersection of two of the observatory’s most active narrative threads: AI chips and technological sovereignty, and the contest between ecosystems over who controls the foundational infrastructure of the AI era.
US export controls imposed in October 2022 — and tightened repeatedly since — restrict China’s access to advanced AI processors (Nvidia’s H100 and successors) and the equipment needed to manufacture leading-edge chips. These controls exploit a structural dependency: Chinese AI developers need chips, and those chips were designed using Western IP and manufactured using Western equipment. RISC-V represents a different path. Because the ISA is genuinely open and governed from Switzerland, it sits outside the reach of US licence revocation. A Chinese chip designer building on RISC-V has no Western intellectual property at the foundational level that can be switched off.
This creates a genuine policy dilemma. In November 2023, a bipartisan group of 18 US lawmakers urged Commerce Secretary Raimondo to restrict China’s access to RISC-V, with Senator Rubio stating that China was “using open-source chip architecture to dodge our sanctions.” The counterargument, made most systematically in a CSIS report by Sujai Shivakumar and Julie Heng (April 2025), is that such restrictions are both technically ineffective (the specification is already published; China already has it) and strategically self-defeating: 12 of 24 Premier Members of RISC-V International are Chinese firms, meaning restriction would remove American companies from the standards body while doing nothing to impede Chinese participation. The CSIS recommendation was the opposite of restriction — deeper US engagement in the standards process itself.
The narrative contest here is a version of one the observatory tracks across many threads: whether openness functions as a commons or as a vulnerability. Different ecosystems give categorically different answers.
Key Facts and Dates
- May 2010: RISC-V project launched at UC Berkeley by Asanović, Waterman, Lee, and David Patterson.
- 2011: ISA specification published as open source.
- 2015: RISC-V Foundation established as a standards body; SiFive founded as the first commercial RISC-V chip company.
- November 2019: Foundation announces relocation to Switzerland, citing geopolitical risk to open collaboration.
- March 2020: Renamed RISC-V International as a Swiss nonprofit business association.
- October 2022: US export controls on advanced AI chips dramatically accelerate Chinese interest in RISC-V as an architectural alternative.
- March 2025: Eight Chinese government agencies release a comprehensive policy framework mandating RISC-V adoption in critical infrastructure and requiring all domestic IoT chips to use RISC-V by 2027 — the first formal government mandate.
- March 2026: Alibaba’s DAMO Academy announces the XuanTie C950, described as the most powerful RISC-V processor yet announced. Built on a 5nm process (fabricator unconfirmed, TSMC reported but not acknowledged), the chip features integrated AI acceleration supporting models including DeepSeek V3 and Qwen3, and achieves single-core performance comparable to Apple’s M1. Notably, Alibaba has not confirmed the manufacturing partner — if TSMC, the chip’s existence reveals that architectural independence does not yet imply manufacturing independence, a tension the observatory’s sources have not resolved.
Projections from CSIS estimate RISC-V chip shipments will grow from approximately 2 billion today to 20 billion annually by 2031, a compound annual growth rate of 33 percent. Nvidia has already shipped over 1 billion RISC-V cores across its products; Qualcomm, over 650 million. The architecture is not a Chinese niche — it is a global shift. China’s strategic advantage is in moving fastest and most deliberately.
Where to Learn More
- RISC-V International — the governing body’s official site, with full specification documents and membership information.
- CSET Georgetown: RISC-V — What It Is and Why It Matters — Jacob Feldgoise, January 2024. Concise policy-oriented primer from a leading technology security research centre.
- CSIS: Sustaining Standards Leadership — The United States Cannot Disengage from RISC-V — Shivakumar & Heng, April 2025. The most current and rigorous policy analysis of the US strategic dilemma.
- The Register: Alibaba delivers RISC-V server chip for Chinese AI — March 2026. Technical coverage of the C950 announcement with geopolitical context.